DDR5 Subtimings Advanced Tuning Guide Beyond XMP
XMP (Intel) or EXPO (AMD) profiles give you a tested, safe overclock with one click in BIOS. They are a massive improvement over JEDEC defaults, but they are not the end of the road. Memory manufacturers build conservatism into XMP profiles to ensure they work across every motherboard that might run that kit. On your specific board with your specific IMC (Integrated Memory Controller), you can almost certainly tighten those timings further — and the performance gains in memory-sensitive workloads are real.
Understanding the Timing Hierarchy
DDR5 timings are organized in three tiers:
Primary Timings (the “big four”)
These appear in every benchmark and BIOS screen:
| Timing | Symbol | What It Controls |
|---|---|---|
| CAS Latency | CL | Cycles from column address to data output |
| RAS to CAS Delay | tRCD | Cycles to activate a row before column access |
| Row Precharge Time | tRP | Cycles to close a row before opening another |
| Active to Precharge | tRAS | Minimum time a row stays open |
Example: DDR5-6000 CL30-38-38-96 means CL=30, tRCD=38, tRP=38, tRAS=96 at 6000 MT/s.
Secondary Timings
These run underneath the primary timings and handle specific memory bus operations:
- tRFC (Refresh Cycle Time): How long a DRAM refresh operation takes. DDR5 uses tRFC1 and tRFC2 — tighter values here improve refresh efficiency.
- tWR (Write Recovery): Cycles after a write before a precharge can occur.
- tRTP (Read to Precharge): Cycles between read and precharge — critical for random access patterns.
- tFAW (Four Activate Window): Limits how many row activates can happen in a sliding window — affects burst bandwidth.
- tRRD_L / tRRD_S: Row-to-row delay within the same (L) or different (S) bank group.
Tertiary Timings
The most granular and board-dependent:
- tREFI: Refresh interval. Extending tREFI (less frequent refreshes) improves bandwidth at the cost of data retention margin.
- tCWL: CAS Write Latency — often set to CL-1 or CL-2.
- tRDRD, tWRWR, tRDWR: Turn-around delays between read/write operations.
Tools for DDR5 Subtiming Analysis
Thaiphoon Burner
Thaiphoon Burner reads your module’s SPD and XMP data, revealing every timing parameter programmed by the manufacturer. This is your starting reference point.
- Download from softnology.biz.
- Launch and click Read → Read SPD (Slot 0).
- Click Report → Generate Report (HTML) for a full timing dump.
- Look for the XMP profile section — every parameter listed is a candidate for tuning.
BIOS Memory Training Tools
Modern BIOS from ASUS (DOCP/XMP section), MSI (OC settings), and Gigabyte (MIT) expose secondary and tertiary timings. Enable Expert Mode or Advanced DRAM Timing to access sub-timing fields.
AIDA64 Memory Benchmark
Use AIDA64’s Memory and Cache Benchmark to measure before/after for each timing change:
- Read bandwidth (GB/s)
- Write bandwidth (GB/s)
- Copy bandwidth (GB/s)
- Latency (ns) — the most critical metric for gaming
MemTest86 and TestMem5
Stability testing is mandatory. Use:
- TestMem5 with anta777’s “Extreme” preset for 2+ hours
- MemTest86 for overnight coverage on aggressive tuning
Safe Tuning Approach
Step 1 — Establish a Stable XMP Baseline
Enable XMP/EXPO in BIOS. Boot into Windows, run AIDA64 benchmark, note all four metrics. Run TestMem5 for 30 minutes to confirm XMP stability. This is your reference.
Step 2 — Tighten CAS Latency
CL is the most impactful primary timing. From your XMP CL value, subtract 2 and test:
- XMP says CL36 → Try CL34
- If stable after TestMem5, try CL32
- If unstable, raise voltage (vDD) by 25 mV increments up to 1.45V on typical DDR5
Tighter CL directly reduces memory latency. Going from CL36 to CL30 at DDR5-6000 can cut latency from ~72 ns to ~60 ns — a 16% improvement.
Step 3 — Balance tRCD and tRP with CL
tRCD and tRP are often set equal to or slightly above CL. Try matching them to your new CL value:
CL30 → tRCD 30 → tRP 30
CL32 → tRCD 32 → tRP 32If the system posts but fails TestMem5, raise tRCD/tRP by 2 before trying to lower CL further.
Step 4 — Tune tRAS
tRAS should generally be set to CL + tRCD + 2 as a starting point, then tested tighter. Many systems tolerate tRAS = CL + tRCD (no extra margin). Avoid setting tRAS below CL + tRCD — this violates DRAM protocol and causes corruption.
Step 5 — Optimize Secondary Timings
After primary timings are stable, address these high-impact secondaries:
tRFC1: Start at XMP value, reduce by 20 ns at a time. Stop at first TestMem5 failure.
tREFI: Start at 65535 (maximum typical BIOS value). Monitor system temperatures — heat increases refresh requirements.
tRTP: Try 12 if XMP says 16. Saves cycles on read-to-precharge transitions.
tFAW: Try 16 if XMP says 32. Very board-dependent.Step 6 — Voltage Margins
DDR5 uses two primary voltages:
| Voltage | Role | Safe Range |
|---|---|---|
| VDD (DRAM core) | Powers memory cells | 1.10V – 1.50V |
| VDDQ (I/O) | Signals between DRAM and controller | Should match VDD on DDR5 |
| VPP (peripheral) | Row activation power | 1.8V – 2.0V, rarely adjusted |
Do not exceed 1.50V VDD without active airflow across the DIMMs. Hynix M-die (common in DDR5 kits) is more voltage-tolerant than Samsung A-die. Check Thaiphoon Burner for your die identification.
Expected Performance Gains
| Config | Memory Latency | Read BW | Write BW |
|---|---|---|---|
| JEDEC DDR5-4800 CL40 | ~82 ns | ~75 GB/s | ~73 GB/s |
| XMP DDR5-6000 CL36 | ~72 ns | ~90 GB/s | ~87 GB/s |
| Tuned DDR5-6000 CL30 | ~60 ns | ~96 GB/s | ~93 GB/s |
| Aggressive DDR5-6400 CL28 | ~52 ns | ~102 GB/s | ~99 GB/s |
In gaming, memory latency improvements show most clearly in CPU-limited scenarios. A 12 ns latency reduction translates to roughly 3–8% higher minimum FPS in titles like Total War: Warhammer III and Civilization VII that hammer system memory constantly.
What Can Go Wrong
- Failure to POST: BIOS saved bad timings. Clear CMOS by removing the motherboard battery for 30 seconds or using the CLR_CMOS jumper.
- Windows crash on boot: Timings accepted by BIOS but failed under OS load. Enter BIOS, raise CL or voltages.
- Intermittent corruption: Passed a short TestMem5 run but failing longer tests. Memory is not stable — do not use these timings for daily driving.
- Increased memory temperatures: Tight tRFC with high tREFI. Reduce tREFI back toward default.
Memory tuning rewards patience. Make one change at a time, test, then proceed. The best DDR5 tuners on forums like SkatterBencher document every step — follow their methodology rather than jumping to aggressive numbers immediately.